1. Field of the Invention
The present invention relates generally to a prefetch monitor and, in particular, to a prefetch monitor for use in an information processing system wherein certain instructions result in the execution of corresponding other sequences of instructions.
2. Description of the Prior Art
As is well known in the art, many information processing systems include, in association with their central processing units, instruction queues for fetching and storing instructions in advance of the execution of the instructions. In certain systems, for example, the instruction queue is comprised of an instruction prefetch queue and a following instruction decode queue. The instruction prefetch queue fetches and stored instructions in advance of their execution and the instruction decode queue effectively pipelines the execution of instructions from the prefetch queue by at least partially decoding the instructions before their actual execution.
As is also well known in the art, most systems also include a mechanism whereby the normal execution of instructions may be interrupted to execute a different sequence of instructions, for example, to service keystroke inputs. In this respect, it should be noted that, as is also well known in the art, interrupts may be divided into two broad classes, that is, maskable interrupts and non-maskable interrupts (NMIs). Expressed simply, maskable interrupts are those wherein the servicing of the interrupt may be deferred until the completion of a currently executing routine, or until some convenient stopping point in the routine. NMIs are essentially those wherein, because of the nature of the occurrence which resulted in the interrupt, the interrupt must be serviced immediately.
In this regard, a class of NMI which is of particular interest in the present invention arises from the operation of a system in emulating the operation of a different system. As is well known, the emulation of a given computer by another computer requires that the emulating computer execute sequences of instructions, that is, programs, originally written for the system to be emulated. In the present example, as is described in detail in related U.S. patent application Ser. No. 629,028, this emulation is performed through operation of NMIs wherein the emulating system detects the occurrence of "foreign" instructions and, when a "foreign" instruction is detected, issues a NMI. The emulating system respnds to such NMIs by selecting and executing an emulation routine which directs the emulating system to perform an operation which emulates the function which would have resulted in the emulated system from that instruction.
If a system pipelines the execution of instructions, an NMI may not take effect during or at the end of execution of the current instruction and the system may execute one or more further instructions before the system responds to the occurrence of the interrupt. In most cases, NMIs are used only for serious events, such as parity errors, wherein the execution of one or more additional instructions is not of serious consequence. That is, the disruption to system operation is of such magnitude that the effort and disruption required to resume execution of the interrupted sequence of instructions is of relatively minor importance.
In certain cases, however, for example in the emulation of another system, the interrupt routine which was executed in response to an NMI should return to normal execution beginning at the instruction following the instruction which resulted in the NMI. If additional instructions are executed, however, the state of operation of the system may be altered such that information required for the execution of the next following instructions is lost or changed and the system may not be able to resume operation at the next instruction. In this regard, the instruction which resulted in an NMI may be regarded as having caused a non-recoverable change in state of the system such that normal execution of following instructions cannot be resumed.
The present invention addresses this and other related problems of the prior art.